![]() ![]() Reference design top-level VHDL file (plain VHDL).VHDL source files (plain or encrypted, depending on product options).Standard AXI Stream interface for user integration.Up to 32 independent DMA channels (up to 16 in each direction).Streaming data transfer between FPGA and host. ![]() Evaluation kits and reference design available.Universal and friendly user space API on Windows and Linux 1.Runs straightforward on Windows and Linux.No need for dealing with complexity of underlying protocols.Complete and easy to use solution for communication between FPGA and host.Configurable user datapath width (64-bit / 128-bit / 256-bit).Supports packet-based or stream-based data transfers.Up to 128K DMA descriptors pre-fetching.Up to 4 GByte data transfer in a single DMA transfer.Supports C, C++ and C#/.NET user applications.Streaming and memory-mapped accesses are supported. The user host application can communicate with the FPGA through a simple API consisting of simple read/write data commands hiding the complexity of the underlying protocols. The solution includes a host software library (DLL/SO), a PCI Express driver, and a suitable IP core for the FPGA. Enclustra’s FPGA Manager PCIe solution is optimized for Intel (Altera) and Xilinx FPGAs and allows for easy and efficient data transfer between a host and a FPGA over a PCI Express interface.
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